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AR# 66974

1G/2.5G Ethernet PCS/PMA or SGMII - UltraScale - Unable to meet timing for SGMII over LVDS solution on UltraScale devices

Description

Why am I unable to meet timing for an SGMII over LVDS solution on UltraScale devices?

Solution

One possible cause is if you have not placed IDELAYs close enough to meet timing and the tool does not do so either. Because idelay_cal is not associated with any I/Os, the tool considers it to be a floating IDELAY and places it randomly.

In the IP there are sample constraints for 2 devices and for other devices, the constraints are commented in the example design XDC as a guidance.

To work around the issue, place all IDELAYs (idelay_cal) in the IP in nearby locations so that you do not face similar timing issues.

AR# 66974
Date Created 04/06/2016
Last Updated 04/13/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2015.4.2
  • Vivado Design Suite - 2015.4.1
  • More
  • Vivado Design Suite - 2015.4
  • Vivado Design Suite - 2015.3
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1
  • Less
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII