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AR# 68924

2017 Vivado IP Flows - Known Issues for Vivado 2017.x IP Flows

Description

This answer record contains known issues for Vivado Design Suite 2017.x related to IP core flows, including IP customization, IP generation, IP Packager, IP Catalog and integration of IP cores into the Vivado design environment.

Solution

Outstanding Known IP Flow Issues in Vivado 2017.3

(Xilinx Answer 60195)Editing a packaged IP in IP Packager and then discarding those edits might not completely remove all HDL file edits
(Xilinx Answer 66285)XSDB message: Cannot stop MicroBlaze. Stalled on instruction fetch
(Xilinx Answer 66982)The Customization GUI of IP offer connection(s) to board components that have already been used in a project
(Xilinx Answer 66984)BRAM memory initialization in a user IP gives, "Critical Warning: [Synth 8-4445] could not open $readmem data file '32x16_rom_init.mem' "
(Xilinx Answer 67850)Validating an IP Integrator block design gives ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
(Xilinx Answer 68010)The out of Context (OOC) runs for a Block Design (BD) go out of date as soon as any Block configuration changes are made
(Xilinx Answer 68293)  write_hwdef and write_sysdef do not write out software drivers from a subcore in a user IP block
(Xilinx Answer 70026)IP cores with multiple license features are not cached
(Xilinx Answer 70165)Synthesizing an Ethernet subsystem IP gives ERROR: [Designutils 20-176] Cannot open XDC file "*_board.xdc"
(Xilinx Answer 70182)Synthesis fails on Video Mixer IP in Block Design; "Synthesis target needs to be generated before calling compile_c."

Known IP Flow Issues Resolved in Vivado 2017.3

(Xilinx Answer 70078)IP Packager is adding extra files to my IP when I manually add a file to a file group
(Xilinx Answer 70080)Upgrade Selected silently fails after changing the project target device
(Xilinx Answer 70081)The yellow banner indicating that an IP instance is out of date does not show in Vivado 2017.2
(Xilinx Answer 70082)Synthesis gives "ERROR : module '<bd_mod>' not found" when synthesizing a BD after changing the target language

Known IP Flow Issues Resolved in Vivado 2017.2

(Xilinx Answer 69443)Abnormal Program Termination for Kintex UltraScale design when running OOC Synthesis on AXI PCIE3 IP core
(Xilinx Answer 70079)Migrating a Vivado project with a BD to Vivado 2017.1 causes module references files to be stale

Known IP Flow Issues Resolved in Vivado 2017.1

(Xilinx Answer 67895)Packaging a BD design that contains a processer, using the "Use Generated Files" option, leads to invalid scoping of constraints
(Xilinx Answer 68275)

After migrating a synthesized design to Vivado 2016.3, the OOC runs of some IP of a Block Design are reset when launching implementation

Linked Answer Records

Child Answer Records

AR# 68924
Date 12/04/2017
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2017.1
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