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AR# 69036

DDR3 UltraScale and UltraScale+ IP Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the DDR3 UltraScale and UltraScale+ Cores and includes the following:

  • Supported Devices
  • General Information
  • Known Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2014.1 and newer tool versions.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

MIG IP Page:

https://www.xilinx.com/content/xilinx/en/products/intellectual-property/mig.html

Solution

General Information

Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

DDR3 VersionVivado Tools Version
v1.4 (Rev. 1)2017.2
v1.42017.1
v1.3 (Rev. 1)2016.4
v1.32016.3
v1.2 Rev12016.2
v1.22016.1
v1.12015.4
v1.02015.3
v7.12015.2
v7.02015.1
v6.12014.4
v6.02014.3
v5.0 Rev12014.2
v5.02014.1

* Starting with the release of Vivado 2015.3, the MIG wizard is no longer used. A separate wizard exists for all supported memory interface types. Therefore, the core versions reset to 1.0.

For a list of supported memory interfaces and features for UltraScale FPGAs, see the LogiCORE IP UltraScale Architecture-Based FPGAs Memory Interface Solutions Product Guide (PG150) located at:

https://www.xilinx.com/products/technology/memory-interfacing/index.htm

For a complete list of supported memory devices please refer to the attached spreadsheet called "memory_device_support_2016_1.xlsx".


For a list of supported frequencies for UltraScale FPGAs Memory Interfaces, see the appropriate DC and Switching Characteristics Data Sheet available in the UltraScale Documentation Center.

For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

The MIG tool includes the appropriate frequency range for each specific memory interface configuration

Table 2 provides answer records for general guidance when using the MIG UltraScale core.

Table 2: General Guidance

Answer RecordTitle
(Xilinx Answer 59625)MIG UltraScale - Design Methodology Checklist
(Xilinx Answer 61304)MIG UltraScale - Clocking Guidelines and Requirements
(PG150) - DebuggingMIG UltraScale DDR4/DDR3 - Hardware Debug Guide
(Xilinx Answer 63462)MIG UltraScale - Sample CSV data file for creating Custom Parts
(Xilinx Answer 63831)MIG UltraScale - Migrating and Upgrading IP into 2015.1
(Xilinx Answer 61598)Design Advisory Master Answer Record for Kintex UltraScale FPGA
(Xilinx Answer 61930)Design Advisory Master Answer Record for Virtex UltraScale FPGA
(Xilinx Answer 62483)Design Advisory for MIG UltraScale (all memory types) - VRP pin and DCI Cascade requirements
(Xilinx Answer 68169)Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs - New minimum production speed specification version (Speed File) required for all designs

Known and Resolved Issues

The following table provides known issues for the MIG UltraScale core, starting with v5.0, initially released in the Vivado 2014.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


MIG UltraScale DDR3 SDRAM

The following table provides known issues for MIG UltraScale DDR3.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 69291)UltraScale+ Memory IP - The SFVA625 package does not support PL Memory Interfacesv1.4v1.4 (Rev. 1)
(Xilinx Answer 68028)UltraScale Memory IP - Pulse width violations occur for designs that violate the maximum BUFGCE timing spec with the Reference Input Clock Speed (ps)v1.3v1.4
(Xilinx Answer 67392)UltraScale and UltraScale+ Memory IP - pulse width violations can occurv1.2 (Rev. 1)v1.4
(Xilinx Answer 67956)DDR4/DDR3 UltraScale IP - Supported configurations for Self Refresh and Save/Restorev1.3v1.3
(Xilinx Answer 66937)DDR4 and DDR3 IP - UNISIM simulations fail when using Self Refresh and Self Restore optionsv1.3v1.3
(Xilinx Answer 67967)UltraScale Memory IP - Error: [Unisim MMCME3_ADV-10] The calculated PFD frequency=799.360512 Mhz. This exceeds the permitted PFD frequency rangev1.3v1.3 (Rev. 1)
(Xilinx Answer 67957)UltraScale Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IPv1.3v1.3 (Rev 1)
(Xilinx Answer 66927)DDR4 and DDR3 IP - BFM simulations have errors when using Self Refresh and Self Restore optionsv1.3
v1.3 (Rev 1)
(Xilinx Answer 67933)UltraScale Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part.v1.3
v1.3 (Rev. 1)
(Xilinx Answer 67544)DDR4/DDR3 UltraScale IP - Data errors seen at user interface when using Normal Ordering Error. The errored data presented is correct data from a later read from the same address. App_rdy might get stuck low.v5.0v1.3
(Xilinx Answer 67891)DDR4/DDR3 IP - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation modev1.2 (Rev. 1)v1.3
(Xilinx Answer 67455)UltraScale DDR3 and DDR4 IP - ECC signals are missing from the User Interface when ECC is enabled without AXIv1.2 (Rev. 1)v1.3
(Xilinx Answer 67684)UltraScale Memory IP - moving IP that uses custom memory parts (CSV) might cause problemsv1.2 (Rev. 1)v1.3
(Xilinx Answer 67335)UltraScale+ Memory IP - devices fail during opt_design with custom memory part if generation of the IP output products is skippedv1.2 (Rev. 1)v1.3
(Xilinx Answer 66360)UltraScale Memory IP - Core Container does not include *.csv file when a custom memory part is createdv1.0v1.3
(Xilinx Answer 67225)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint not automatically generated by IPv1.2v1.2 (Rev. 1)
(Xilinx Answer 67224)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint must be applied to the CLKIN1 pin of the MMCMv1.2v1.2 (Rev. 1)
(Xilinx Answer 67164)UltraScale+ Memory IP - timing failures occur due to high congestion levelsv1.2v1.2 (Rev. 1)
(Xilinx Answer 66678)UltraScale Memory IP - Design fails during 'opt_design' when using Custom CSV
v1.2v1.2 (Rev. 1)
(Xilinx Answer 65083)DDR4/DDR3 SDRAM IP - No DIMM support for XCZU2EG and XCZU3EG devices with the SBVA484 packagev1.0v1.2 (Rev. 1)
(Xilinx Answer 66794)UltraScale DDR3 IP - Write errors may be seen in dual rank or dual slot configurations in Vivado 2015.3 or 2015.4 due to Dynamic ODT settingsv1.0v1.2
(Xilinx Answer 65950)
MIG UltraScale DDR4/DDR3 - Synplify PRO Synplify Pro Black Box Testing designs may fail in calibrationv1.0v1.2
(Xilinx Answer 65421)UltraScale DDR3 - tIS memory model violations on ADDR and BA occur when simulating DDR3 example_tb testbenchv6.0v1.2
(Xilinx Answer 62543)MIG UltraScale - Certain speed grades incorrectly prevent previously allowed input clock periodsv6.0v1.2
(Xilinx Answer 65431)UltraScale Memory IP - Designs generated pre-v1.0 with "No Buffer" clocking option require path update to CLOCK DEDICTAED ROUTE constraintv1.0NA
(Xilinx Answer 65327)UltraScale Memory IP - CRITICAL WARNING: [Xicom 50-38] xicom: The current version of Vivado does not support this detected version of the MIG core. 2015.2 is the last version supporting it.v1.0NA
(Xilinx Answer 64778)MIG UltraScale - When using the Auto Assign feature of Bank Planner, an error message is not issued when the memory ports do not fit into a half bankv7.0v1.1
(Xilinx Answer 65370)Memory IP - pblocks containing UltraScale Memory IP logic must be contained within the same clock region the memory IO is located inv1.0v1.1
(Xilinx Answer 65493)DDR4/3 UltraScale - IP generation fails for configurations requiring more than 3 contiguous banks when targeting FGPA devices with half banks in between full banksv1.0v1.1
(Xilinx Answer 65790)DDR4/DDR3 SDRAM IP - when using a Custom Memory part some timing parameters are not updated correctlyv1.0v1.1
(Xilinx Answer 65652)DDR3/DDR4 SDRAM IP - AXI enabled designs incorrectly have data mask tied to GND during Read-Modify-Writev1.0v1.1
(Xilinx Answer 65372)DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulatorv1.0v1.1
(Xilinx Answer 64856)Design Advisory for UltraScale DDR4/DDR3 - PCB pull-down required on the DDR3 RESET# pin and on the DDR4 RESET_N pin to maintain logic low during memory initialization Initial Releasev7.1
(Xilinx Answer 64188)MIG UltraScale - sys_rst missing set_false_path constraintv7.0v1.1
(Xilinx Answer 62086)MIG UltraScale DDR4/DDR3 - Performance Traffic Generator only works with "ROW COLUMN BANK" Address mappingv5.0 Rev1v1.1
(Xilinx Answer 65261)MIG UltraScale DDR4/DDR3 - Dynamic DCI does not work for select devicesv7.1v1.0
(Xilinx Answer 64775)MIG UltraScale DDR3 - tZQinit violations seen during DDR3 simulationsv7.1v1.0
(Xilinx Answer 64923)MIG UltraScale - [Xicom 50-24] error message occurs after programing devicev7.0v1.0
(Xilinx Answer 64773)MIG UltraScale DDR4/DDR3 - customization GUI shows incorrect Enable Chip Select Pin option when recustomizing IPv7.0v1.0
(Xilinx Answer 63787)MIG UltraScale DDR3 - ERRORs in simulation are seen when using Micron memory model for sg125 speed grade with CAS latency = 9 and CAS Write Latency = 7v7.0v1.0
(Xilinx Answer 64071)MIG UltraScale - custom memory parts fail simulationv7.0v1.0
(Xilinx Answer 63852)MIG UltraScale DDR3 - Usage of HR banks requires user to update the output_impedance of all ports using reset_property commandv7.0N/A
(Xilinx Answer 64410)UltraScale DDR3 IP - Can either external or internal Vref be used? There is no option within the MIG tool.v7.0N/A
(Xilinx Answer 64655)DDR3 UltraScale - Dual Rank RDIMM - IP generation incorrectly enables address mirroring for dual rank DDR3 RDIMMsv7.0v7.1
(Xilinx Answer 64010)MIG UltraScale DDR4/DDR3 - memory controller may hang when in "Strict" modevv7.0v7.1
(Xilinx Answer 64146)MIG UltraScale DDR3 - simulation warnings for 16Gb and 8Gb DDR3 TwinDie partsv7.0v7.1
(Xilinx Answer 64069)MIG UltraScale - The Memory Byte/Bank Planner does not honor previously set PROHIBIT pinsv7.0v7.1
(Xilinx Answer 64063)MIG UltraScale DDR4/3 - DIMM tool tip incorrectly lists the density for the base component partv7.0v7.1
(Xilinx Answer 63789)MIG UltraScale DDR3/DDR3L (HR banks only) - It is required to target a memory device that is one speed grade faster than the target datarate when using UltraScale -2/-3 speed grades within HR banksv7.0v7.1
(Xilinx Answer 63261)MIG UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during Lint checkv6.1v7.0
(Xilinx Answer 64431)MIG UltraScale - ]Xicom 50-38] xicom: Invalid memory type value detected from MIG core: 0.v6.1v7.0
(Xilinx Answer 63596)MIG UltraScale - HOLD violations may be seen when using 2014.4.1v6.1v7.0
(Xilinx Answer 64070)MIG UltraScale - designs with multiple controllers may generate ERROR::34 messagev6.1v7.0
(Xilinx Answer 63240)MIG UltraScale DDR4/DDR3 - PHY Only Documentation - PG150 includes incorrect usage of "rdDataEn" in relation to "per_rd_done" (periodic read operation) and "rmw_rd_done" (RMW Operation)v6.1v7.0
(Xilinx Answer 62930)MIG UltraScale DDR3/DDR4 - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurationsv6.1v7.0
(Xilinx Answer 62776)MIG UltraScale DDR3/DDR4 - ECC fault injection does not workv6.1v7.0
(Xilinx Answer 62774)MIG UltraScale - timing failures may be seen with MIG generated example designv6.1v7.0
(Xilinx Answer 62649)MIG UltraScale - GUI allows core generation even if all address and control byte lanes have not been selectedv6.0v7.0
(Xilinx Answer 59989)MIG UltraScale - Critical warnings are generated when multiple MIG instances are included in a designv5.0v7.0
(Xilinx Answer 60528)MIG UltraScale DDR3 - Vivado may fail to generate output products with 64-bit data widthv5.0v7.0
(Xilinx Answer 59991)MIG UltraScale - When running QuestaSim simulation within the Vivado GUI, the simulation is not successful.v5.0v7.0
(Xilinx Answer 59990)MIG UltraScale - IPI MIG simulation does not have memory models availablev5.0v7.0
(Xilinx Answer 61076)MIG UltraScale - Multiple instances of MIG IP fail with "[Place 30-678] Failed to do clock region partitioning"v5.0 Rev1v6.1
(Xilinx Answer 62321)MIG UltraScale DDR3/DDR4 - User Interface ports direction incorrect in instantiation templatev5.0v6.1
(Xilinx Answer 62050)MIG UltraScale DDR4/3 - Can reset_n be allocated to an I/O or does it have to be within a memory interface bank?v5.0v6.1
(Xilinx Answer 61909)MIG UltraScale DDR3/DDR4 - app_wdf_data format clarificationv6.0v6.1
(Xilinx Answer 61901)MIG UltraScale DDR3/DDR4 - memory model violations observed during simulationv5.0 Rev1N/A
(Xilinx Answer 61696)MIG UltraScale - the funcsim.v/.vhdl structural simulation model is not supportedv5.0 Rev1N/A
(Xilinx Answer 61129)MIG UltraScale DDR3 - "ERROR: tCK(avg) minimum violation"v5.0 Rev1v6.0
(Xilinx Answer 61988)MIG UltraScale DDR4/3 - Hold violations may be seen on a path clocked by riu_clkv5.0 Rev1v6.0
(Xilinx Answer 60953)MIG UltraScale - Output Products must be generated before opening the IP Example Designv5.0 Rev1v6.0
(Xilinx Answer 59948)MIG UltraScale DDR4/DDR3 - Incorrect clock connection on dbg_hub which can have a negative timing impactv5.0v 5.0 Rev1

Revision History:

04/18/2017Created Separate Answer Record for DDR3
06/12/2017Updated for 2017.2; Added AR68028, AR69291

Attachments

Associated Attachments

Name File Size File Type
memory_device_support_ddr3.xlsx 18 KB XLSX

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues N/A N/A
AR# 69036
Date 06/20/2017
Status Active
Type Release Notes
Tools
  • Vivado Design Suite
IP
  • MIG UltraScale
  • DDR3 SDRAM
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