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AR# 71389

2018.2.1 Vivado - Vivado 2018.2 Update 1 (2018.2.1) Release Notes and Known Issues

Description

This answer record serves as the Vivado 2018.2 tool update 1 (2018.2.1) Release Notes, and contains links to information about what is included in the update.

Solution

The Vivado 2018.2 tool update 1 (2017.2.1) addresses the following issues:

Vivado 2018.2 Update 1 provides:

Production Devices:

Zynq UltraScale+ MPSoC (-3) Devices

  • XCZU4EG/EV, XCZU5EG/EV, XCZU6EG, XCZU7EG/EV, XCZU9EG
Kintex UltraScale+ FPGA (-3) Devices:

  • XCKU9P
Zynq UltraScale+ RFSoC (-1L, -2LI) Devices:

  • XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, XCZU29DR

Spartan-7 Devices:

  • XC7S75(-1Q), XA7S75 (-1,-2,-1Q), XC7S100(-1Q), XA7S100 (-1,-2 -1Q) , XA7S6(-1, -2, -1Q), XA7S15(-1, -2, -1Q)
New devices enabled in WebPack:

  • Spartan-7: XC7S75, XA7S75, XC7S100, XA7S100, XA7S6, XA7S15

For customers using these devices, Xilinx recommends installing Vivado 2018.2.1.

For other devices, please continue to use Vivado 2018.2.

Downloading and installing the Vivado 2018.2 update (2018.2.1)

  • The update is available at: https://www.xilinx.com/download
  • It must be applied to an existing 2018.2 (SW Build 2258646 ) installation, and will bring the Vivado version to 2018.2.1.


Known Issues specific to Vivado 2018.2 update 1 (2018.2.1)

  • For Memory IP, please see (Xilinx Answer 71391) for timeline updates and integration support for projects using -2LI RFSoC parts
  • For Vivado 2018.2 known issues see: (Xilinx Answer 70860)
  • For known issues related to a specific IP, please search the support site for "Known Issues" and the IP name.
AR# 71389
Date 08/03/2018
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2018.2.1
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