UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7172

Virtex JTAG - How do I perform a readback verify on Virtex devices?

Description

Urgency: Hot

General Description:

What are the steps required to do a readback on the Virtex devices?

Solution

To perform a readback, follow these steps using your own software:

1. Load the CFG_IN instruction into the JTAG IR, then go to SDR.

2. Shift in a packet to write the starting frame address into the FAR. For a full-chip readback, this is frame 0 of CLB column 0.

3. Shift in a packet to write the RCFG command into the CMD register.

4. Shift in a packet header requesting a read of the Frame Data Output Register (FDRO). The word count should reflect the number of frames you wish to read. If the number of words exceeds 2048, you must use a two-part header (i.e., Type I followed by Type II).

5. Shift in an extra 32 bits. These are to flush the pipeline through the packet processor. Then, return to RTI.

6. Load the CFG_OUT instruction into the JTAG IR, then go to the SDR.

7. Clock TCK and read TDO. There will be a few meaningless 32-bit words before the readback data appears.

8. If you wish to read the Block RAM (BRAM) data as well as the CLB data, repeat steps 1-7, substituting the appropriate BRAM address for the starting CLB address. Each BRAM must be addressed individually. Note that a BRAM readback will interface with BRAM operation in an active system. It is therefore recommended that the system be halted prior to BRAM readback.

The Xilinx JTAG Programmer software version 3.2i and newer support readback

verify for Virtex devices.

AR# 7172
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article