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AR# 9838

XST - "WARNING: Xst:766 - file_name (Line #). Generating a Black Box for component "

Description

When a "black box" is instantiated, the following warning occurs: 

 

WARNING: Xst:766 - file_name (Line #). Generating a Black Box for component <component_name>.

Solution

A black box is any instantiated component that is not represented by HDL code, but rather by another netlist format. 

Synthesis tools will generally report some kind of warning when a black box (an instantiated component with no associated VHDL code) is detected.  

 

Examples of black boxes include: 

  • CORE Generator modules 
  • Instantiated EDIF files 
  • Instantiated primitives 

 

If you are instantiating a component that is represented by something other than HDL code, no response to the warning message is needed.

If your intent was not to instantiate a black box, check your component declaration and instantiation to ensure that the component is properly represented by HDL code. 


To avoid "black box" warning messages, add the following lines to your HDL code: 

 

VHDL: 

architecture <architecture_name> 

 

attribute box_type : string; 

attribute box_type of <component_name> : component is "black_box"; 

 

begin 

 

Verilog: 

 //synthesis attribute box_type <module_name> "black_box"

AR# 9838
Date Created 08/21/2007
Last Updated 09/12/2014
Status Active
Type General Article
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
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  • ISE Design Suite - 11.3
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  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13.1
  • ISE - 8.1i
  • ISE - 8.1i sp1
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  • ISE - 8.1i sp3
  • ISE - 8.2i
  • ISE - 8.2i sp1
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  • ISE - 8.2i sp3
  • ISE - 9.1i
  • ISE - 9.1i sp1
  • ISE - 9.1i sp2
  • ISE - 9.1i sp3
  • ISE - 9.2i
  • ISE - 9.2i sp1
  • ISE - 9.2i sp2
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