Description

General Description:

The Virtex PCI LogiCORE unexpectedly asserts the REQ# signal after the bus master bit is set in the Command/Status register.

(The Command/Status register is located in the PCI Configuration Space Header.)

Solution

This will occur if the REQUEST user application signal is asserted before the bus master control bit is set. The Virtex PCI LogiCORE stores the most recent REQUEST from the user application after reset is de-asserted.