2. Support
  3. AR# 1078: ModelSim (MXE, SE, PE) - How do I run a functional (behavioral) simulation with ModelSim stand-alone? (VHDL, Verilog)
  4. AR# 10784: 12.1 Timing/PAR - An "Out of memory" failure occurs during timing analysis (INFO:Timing:2697...or Timing:2802...)

AR# 10784

12.1 Timing/PAR - An "Out of memory" failure occurs during timing analysis (INFO:Timing:2697...or Timing:2802...)

Description

My design runs out of memory during initial timing analysis. The timing analysis ran for hours at a flat level of 400 Mb before running out of memory on a 1 Gb machine in a matter of minutes. How do I change this?

Solution


You can prevent this problem by ensuring that your design is constrained efficiently.

This behavior can be caused by Synplicity writing hundreds of redundant path TIG constraints, which can cause memory usage to increase rapidly. When the TIGs are consolidated into just two constraints, memory usage returns to normal (~400 Mb).

You can consolidate multiple "OFFSET OUT 10 nS AFTER" constraints into one "OFFSET OUT 10 nS AFTER" with a time group. Several more constraints can be consolidated in similar fashion.

For more information, see (Xilinx Answer 12325) and (Xilinx Answer 11749).
AR# 10784
Date 05/13/2012
Status Active
Type Known Issues
Tools More Less