AR# 11556: 14. Timing - What do the various design statistics in a timing report mean (minimum period)?
14. Timing - What do the various design statistics in a timing report mean (minimum period)?
A timing report (design statistic) is created after the Timing Analyzer launches. The design statistics account for terms such as:
- The maximum frequency of the design (minimum period) - The maximum combinational path delay - The maximum net delay
Does the "minimum period" refer to the entire design?
Is the "period check" from two flip-flops with the same clock?
Is the "period check" from two flip-flops with the same rise clock?
How is "maximum combinational path delay" calculated?
What is the difference between the "maximum combinatorial path delay" and the "maximum net delay"?
Yes, theminimum period refers to the entire design. This line indicates the maximum clock frequency at which your design can run.
Yes, the period is checked from two flip-flops with the same clock (Highest clock).
Path and Net Term Definitions:
Path - An ordered set of elements identifying a logic flow pathway through a circuit. A path can consist of a single net or a grouping of related nets and components. Multiple paths (consisting of nets and components) can exist between the two pins.
When a component is selected as part of a path, both the input pin to the component and the output pins are included in the path. A path stops when it reaches the data input of a synchronous element (flip-flop) or pad. A path usually begins at the output of a synchronous element or pad.
Net - A logical connection between two or more symbol instance pins. After routing, the abstract concept of a net is transformed to a physical connection called a "wire."
The above definitions indicate that a path can consist of a single net or a grouping of related nets and components. The maximum combinatorial path delay is calculated as an estimation of the sum of all combinatorial time (delays) for each combinatorial stage in a path. Consequently, the maximum net delay is an estimation of the maximum connection time (delay) between two or more instance pins.