My design includes 3-state buffers (TBUFs) driving a module port, and during the initial/active implementation flow, errors similar to the following are reported:
"ERROR:NgdBuild:705 - The net '<netname>' requires that context logic to be connected to it due to a bidirectional port being used on one of the modules connected it to another module."
"ERROR:NgdBuild:456 - logical net '<netname>' has both active and 3-state drivers."
To avoid the errors above, follow these basic guidelines:
1. If at all possible, place all 3-state buffers in the top-level design.
2. If a 3-state buffer is internal to a module and is driving out to a top-level or other module, the module port associated with that 3-state buffer (TBUF) must be declared as "INOUT". (This is necessary for the Modular Design flow to correctly interpret the signal as a 3-state signal.)
3. On the top level, at least one TBUF must drive the same 3-state signal as the module's TBUF.
4. At least one TBUFs per signal must be LOC'd to a TBUF site during the "Initial Budgeting" implementation, and the UCF must be used in subsequent active and final assembly implementations. (Since a 3-state signal drives a long line, only a TBUF driving the same 3-state signal can be in the same row. This is necessary to avoid contention between the 3-state signals.)
NOTE: If all top-level TBUFs are not LOC'd, NGDBuild issues the following warning during active or final assembly:
"Warning:NgdBuild:706 - TRI primitive '<primitive_name>' should have a LOC constraint attached using the Floorplanner after initial budgeting."
5. If you must modify your design to adopt this change, you must rerun all of the modular design flow, including synthesis, initial budgeting, active, and final assembly implementation.
The following figures illustrate possible cases: