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AR# 13024

12.1 Timing - How are Tdllino and Tdcmino calculated for a DLL/DCM/PLL/MMCM? What does a negative clock path mean?

Description

How are Tdllino and Tdcmino calculated for the DCM? What does a negative clock path mean?

Solution


Tdllino and Tdcmino are determined during the application run time by the design configuration of the DLL and DCM. They are negative delays applied to the clock path to adjust the clock at the registers so that it is in phase with the internal or external clock source.
The calculation of the delay follows this formula:
Tdcmino = - (Tbufgmux + Tfeedback + Tdcmfboffset - Tdcmclkinoffset)
where:
Tbufgmux = The delay from the output of the DLL/DCM to the output of the global clock buffer driving the clock signal used to feed back to the CLKFB pin of the DLL/DCM. If more than one BUFGMUX is used in the feedback path, the delay is equal to the total path delay to the output of the final BUFGMUX.
Tfeedback = The net delay of the signal connecting the output of the global clock buffer and the CLKFB pin of the DLL/DCM.
Tdcmfboffset = A compensation offset used to account for the delay from the IOB to the DLL/DCM.*
Tdcmclkinoffset = A compensation offset fixed to account for other circuit anomalies.** This number is dependent upon circuit conditions and low-level speed file parameters.
(For Virtex/Virtex-E, replace references to "BUFGMUX" with "BUFG".)
This can result in a negative clock delay path, as shown below:
Clock Path: clki to fdc_in0
Delay type..................Delay(ns) Logical Resource(s)
--------------------------------------------------------------------------------------
Tiopi............................0.825 clki
....................................clk_ibufg
net (fanout=1)..............0.798 clk_int
Tdcmino......................-4.362 dcm_0
net (fanout=1)..............0.852 clk_dcm
Tgi0o...........................0.209 clk_bufg
net (fanout=6)..............1.067 clk
--------------------------------------------------------------------------------------
Total............................-0.611 ns (-3.328 ns logic, 2.717 ns route)
This negative delay is normal and correct. The I/O timing may be modified with a fixed phase shift of the DCM, which adjusts the clock arrival time of the clock in static timing analysis. Using different I/O standards for the clock input also yields different clock path delays.
This means that the clock will arrive at the flip-flop before it arrives at the GCLK pin. This ensures a zero hold time, eliminating the need to hold data after the CLK has toggled at the GCLK pin.
For more details on timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug612.pdf
AR# 13024
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 11.1
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