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AR# 13824

Virtex-II DCM - Is a timing diagram that illustrates variable phase shift (DPS) available? (Timing parameter for PSEN, PSINCDEC, PSCLK, and PSDONE)

Description

Is a timing diagram that illustrates variable phase shift available?

Are timing parameters (setup/hold and clock-to-out) for PSINCDEC, PSCLK, and PSDONE with respect to PSCLK available?

Solution

The following timing diagram illustrates variable phase shift:

DFS Variable Mode Timing Diagram
DFS Variable Mode Timing Diagram

As shown above, all variable phase-shift control and status signals are synchronous to the rising edge of PSCLK.

Specific timing parameters for PSINCDEC, PSEN, PSCLK, and PSDONE are not available. Since timing relative to PSCLK is 100% synchronous, PSEN, PSINCDEC, and PSDONE must be registered by PSCLK (rising edge) to ensure correct functionality.

PSEN must be active for exactly one clock period, otherwise, a single increment/decrement of phase shift is not guaranteed.

PSDONE is High for exactly one clock period when the phase shift is complete. The time required for a complete phase shift will vary. As a result, PSDONE must be monitored for phase-shift status.

Between enabling PSEN until PSDONE is flagged, the DCM output clocks will slide bit by bit from their original phase shift to the incremented phase shift. The increment/decrement will be ready by PSDONE.

NOTE: When PSEN is triggered after the phase shift counter has reached the maximum value (255), the PSDONE will still be High for one PSCLK period some time after the PSEN is triggered (as illustrated in the figure above). However, the "Phase Shift Overflow" pin (STATUS(0)) will be High to flag this condition, and no phase adjustment is performed.

Please see (Xilinx Answer 12378) for more information about the (STATUS(0)) pin.

Please see (Xilinx Answer 10972) for more information about other DCM STATUS pins.

AR# 13824
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article