What is the operational level of voltage on the input of an FPGA?
The following information applies to Xilinx 5V FPGAs and all CPLD devices.
Maximum DC overshoot or undershoot above VCC or below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins might undershoot to -2.0V or overshoot to VCC + 2.0V, provided this overshoot or undershoot lasts less than 20 ns.
There are very strong ESD-protection diodes (impedance = 1 Ohm) to help insure these voltage levels are not violated internally. Typical diode currents increase from several microamps at 0.7V to 100 mA at 1V.
Negative voltages are clamped. Excess positive input voltage may pull VCC high. Xilinx suggests controlling the input current to stay below 10 mA constant current. The protection diodes can handle 100 mA without problems; however, if this amount of current is maintained for an extended period of time, the diodes will heat up and effect the surrounding circuitry.
For information on specific devices, see the latest reliability data on the Web at: