line xx Macro '' redefined"">


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AR# 16463

XST - "WARNING:HDLCompilers:38 - line xx Macro '' redefined"


General Description:

When a macro that has previously been defined is presented to the XST Verilog compiler again, the following warning occurs:

"WARNING:HDLCompilers:38 - <file> line xx Macro '<name>' redefined."

This typically happens when a file containing a set of macros is read in multiple times using `include statements.


The compiler presents these messages to ensure that you are aware of the macro redeclaration, in the event that you do not want this to happen.

It is difficult for the compiler to determine whether the new declaration is new or redundant, as macro definitions can come from different places or be made up of other declarations or variables. To be safe, XST will always present the warning when a redeclaration is performed.

To avoid these redundant messages, use the conditional compilation controls to make the compiler aware that these macros have already been defined.

For example, suppose you want to declare a constant width:

`define WIDTH 32

If this is referenced in a file that is called by multiple Verilog modules using an `include statement, the above warning will be reported for each instance beyond the first. You can use conditional compilation to instruct the compiler to determine whether the macro has been previously defined:

`ifndef WIDTH

`define WIDTH 32


You can place as many macros as you want within the `ifndef and `endif statements, and create the `ifndef statement to reference any one of the included macros.

AR# 16463
Date 12/15/2012
Status Active
Type General Article
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