AR# 17772

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7.x Synplify - When instantiating a IBUFGDS_LVPECL_25 Synplify adds an extra IBUFs on the input

Description

General Description:

When instantiating a IBUFGDS_LVPECL_25 using Synplify, NGDBUILD errors with:

"ERROR:NgdBuild:455 - logical net 'ck133_n_c' has multiple drivers. The possible

drivers causing this are pin O on block ck133_n_ibuf with type IBUF, pin PAD

on block ck133_n_c with type PAD

WARNING:NgdBuild:463 - input pad net 'ck133_n_c' has an illegal input buffer

ERROR:NgdBuild:466 - input pad net 'ck133_n_c' has illegal connection. Possible

pins causing this are pin O on block ck133_n_ibuf with type IBUF

ERROR:NgdBuild:455 - logical net 'ck133_c' has multiple drivers. The possible

drivers causing this are pin O on block ck133_ibuf with type IBUF, pin PAD on

block ck133_c with type PAD

WARNING:NgdBuild:463 - input pad net 'ck133_c' has an illegal input buffer

ERROR:NgdBuild:466 - input pad net 'ck133_c' has illegal connection. Possible

pins causing this are pin O on block ck133_ibuf with type IBUF"

Solution

The work-around is to add extra synthesis directives telling Synplify not to add the extra IBUF components:

VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity top is

Port ( c_p : in std_logic;

c_n : in std_logic;

d : in std_logic;

q : out std_logic);

end top;

architecture Behavioral of top is

component ibufgds_lvpecl_25

port (i, ib: in std_logic;

o: out std_logic);

end component;

signal clk: std_logic;

attribute syn_black_box : boolean;

attribute syn_black_box of ibufgds_lvpecl_25 : component is true;

attribute black_box_pad_pin : string;

attribute black_box_pad_pin of ibufgds_lvpecl_25 : component is "i,ib";

begin

u1: ibufgds_lvpecl_25

port map (I => c_p, IB => c_n, O => clk);

process(clk)

begin

if clk='1' and clk'event then

q <= d;

end if;

end process;

end Behavioral;

The work-around is to add extra synthesis directives telling Synplify not to add the extra IBUF components. Unfortunately, for the Verilog solution to work, you must run Synplify in stand-alone mode as ISE automatically adds all of the primitives to the project causing a conflict with the empty module primitive that is made:

Verilog

module top(c_p, c_n, d, q);

input c_p, c_n, d;

output q;

reg q;

wire clk;

IBUFGDS_LVPECL_25 u1

(.I(c_p), .IB(c_n), .O(clk));

always @(posedge clk) q <= d;

endmodule

module IBUFGDS_LVPECL_25 (I, IB, O) /* synthesis syn_black_box black_box_pad_pin = "I, IB" */;

input I, IB;

output O;

endmodule

AR# 17772
Date 12/15/2012
Status Active
Type General Article
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