AR# 18229

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XST - "ERROR:HDLParsers:1411 - Parameter count of mode out cannot be associated with a formal parameter of mode in"

Description

When synthesizing a VHDL design, the following error might occur:

"ERROR:HDLParsers:1411 - <file>.vhd Line xx. Parameter count of mode out cannot be associated with a formal parameter of mode in."

Solution

This error will occur when the output port of a VHDL entity is used to assign a value internally. Consider the following example:

<code>

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test is

port ( clk : in std_logic;

count : out std_logic_vector(7 downto 0));

end test;

architecture Behavioral of test is

begin

process (clk)

begin

if clk='1' and clk'event then

count <= count + 1;

end if;

end process;

end Behavioral;

</code>

This code will fail because "count" is defined as an output signal, but is used to assign a value to itself within the process.

To avoid the error, use an intermediate signal within the process, then assign that signal to an output signal afterwards. For example:

<code>

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test is

Port ( clk : in std_logic;

count : out std_logic_vector(7 downto 0));

end test;

architecture Behavioral of test is

signal count_temp : std_logic_vector(7 downto 0);

begin

process (clk)

begin

if clk='1' and clk'event then

count_temp <= count_temp + 1;

end if;

end process;

count <= count_temp;

end Behavioral;

AR# 18229
Date 12/15/2012
Status Active
Type General Article
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