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AR# 18605

XST - How does XST handle unconnected ports and initial conditions in VHDL?


How does XST handle initial conditions? How does XST handle unconnected ports?


XST initializes memory elements based on the signal initialization value, as shown in the following illustration:

Flip-flop with Initial Value
Flip-flop with Initial Value

The above example puts an initial state of "1" on the reset flip-flop that will be inferred on signal "q". When the FPGA is finished configuring, the flip-flop on signal "q" is in the "1" state even though it is a reset flip-flop. If signal "q" is not initialized to "1", then XST assigns a default of "0" as its initial state. In this case, XST is not following the IEEE standard (where "U" is the default for std_logic) because every memory element in Xilinx FPGAs must come up in a known state.

Where possible, XST adheres to the VHDL IEEE standard when initializing signal values. If initial values are not supplied, then XST uses the default values (where possible) as outlined in the Language Reference Manual:

Initial Value Table
Initial Value Table

Output/inout/buffer ports that are left unconnected default to the values noted above. If the ports have an initial condition, then the unconnected ports are tied to the explicitly defined initial condition. Input ports cannot be left unconnected according to the IEEE specification. As a result, XST always reports an error if an input port is not connected. Even the "open" keyword does not suffice for an input port.

AR# 18605
Date 12/15/2012
Status Active
Type General Article
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