Why are there no Global Clock buffers inferred in my System Generator for DSP design when synthesizing my design?
This problem usually occurs when there is no synthesizable code in your design. Since System Generator for DSP uses cores, a design can consist of only core netlists that are stitched together with HDL. Some synthesis tools cannot read in a netlist, but can only recognize them as a black box, and cannot determine if a clock buffer is needed.
You can work around this issue by using XST with the read cores option turned on. You can also check the documentation for your synthesis tool to see if it can read in a netlist. If this option is not available, then you can work around this by adding some clocked logic HDL)to your design so that the synthesis tool will add a global clock buffer.