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AR# 18993

7.1i CPLDFit - "ERROR:Cpld:1106 - Signal 'SCLK' attached to BUFG drives both an active-high and active-low CLOCK"


General Description:

My CoolRunner-II design utilizes the clock divider. During implementation, errors similar to the following are reported:

"ERROR:Cpld:1106 - Signal 'SCLK' attached to BUFG drives both an active-high and active-low CLOCK. Cannot assign all BUFG nets to global controls.

ERROR:Cpld:887 - Cannot fit the design into this device."


This error message is valid for XC9500 devices in which a single input clock is used to clock separate registers on the rising edge as well as the falling edge. In the XC9500 architecture, this requires two global clock nets since there is no local inversion at each register.

This error message might occur in CoolRunner-II designs where active-high and active-low latches are driven by the output of a clock divider. This is an allowable configuration, so the messages are incorrect.

This problem has been fixed in the latest 6.2i Service Pack, available at:

The first service pack containing the fix is 6.2i Service Pack 1.

AR# 18993
Date 12/15/2012
Status Active
Type General Article