Normally, to infer a global buffer for a top-level signal, that signal must be connected to the clock input of at least one flip-flop. In Modular Design, there are times when the top-level design is made entirely of black-boxes, and there are no flip-flops for the clock signal to drive. This can result in the following types of warnings when local routing is used for a clock:
"WARNING:XdmHelpers:625 - No instances driven from signal "clk" are valid for
inclusion in TNM group "clk". A TNM property on a pin or signal marks only
the flip-flops, latches and/or RAMs which are directly or indirectly driven
by that pin or signal."
"WARNING:Place:410 - The input design contains local clock signal(s). To get the
better result, we recommend users run map with the "-timing" option set
before starting the placement."
For Modular Design, you might have to specify which signals are clocks by either instantiating the global buffers or using synthesis constraints. How can this be accomplished with the various synthesis tools?
You can use the syn_isclock constraint to specify that one of the black-box ports is a clock. In turn, this allows Synplify to recognize that the attached signal is a clock. For more information on the syn_isclock constraint, refer to (Xilinx Answer 1561).
To use an IBUFG -> DLL -> BUFG connection, you might need to use the xc_clockbuftype constraint. Refer to (Xilinx Answer 688) for more information.
You can use the clock_buffer constraint to specify which signals should be using global_buffers.
For more information on using the "clock_buffer" attribute, refer to the latest version of the XST User Guide and the Constraints Guide, which you can access at:
You can use the buffer_sig constraint to specify which signals should be using global buffers. For more information on how to use the buffer_sig constraint, refer to Solution 2 of (Xilinx Answer 4330).