AR# 19500

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6.2 System Generator for DSP - Why is one of my clock (CLK)/clock enable (CE) ports missing when I import my HDL as a black box into System Generator for DSP?

Description

Why is one of my clock (CLK)/clock enable (CE) ports missing when I import my HDL as a black box into System Generator for DSP?

Solution

If the two clocks or clock enables are set to the same rates, the block_interface_wrapper file created for HDL CoSim omits one of the clock/clock enable pairs.

It the clock and clock enable ports are to be run at the same rate, you can work around this issue by connecting the 2 clocks and the 2 clock enables together in the HDL, creating a single clock/clock enable pair.

This issue is resolved in System Generator for DSP 6.3.

AR# 19500
Date 12/15/2012
Status Active
Type General Article
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