When I/O signals are not properly terminated, the FPGA can be exposed to overshoot and/or undershoot. How does this affect the device?
With the exception of JTAG pins in Virtex-II Pro and Virtex-4, all Virtex-II/-II Pro/-4 I/Os have ESD protection diodes to VCCO and Ground that turn on when an I/O signal is 500-600 mV above VCCO or below Ground.
Overshoot and undershoot can damage the FPGA in the following two ways:
- The maximum input gate voltage (Vin) can be exceeded. You must adhere to the absolute maximum specifications in the device data sheets. If these specifications are violated, even for extremely brief periods of time, device reliability cannot be guaranteed.
- The clamp diodes can be exposed to excessive current. They are designed to sink/source 60 mA DC, and they can withstand continuous transient current spikes (e.g., a clock signal) of up to 100-120 mA. Exceeding these limits can lead to damage.
Besides potentially damaging the FPGA, overshoot and undershoot can lead to functional failure. Overshooting signals activate the power clamp diode and sink current into VCCO, which causes noise, jitter, and timing problems. Undershooting signals can cause Block RAM errors.
Overshoot and undershoot can also lead to duty-cycle distortion or inter-symbol interference (data-dependent jitter). When an output driver begins its transition while the I/O signal is above VCCO or below Ground, a timing imperfection (jitter) will result.