When I try to generate a bitstream for Spartan-3E, I receive the following error message:
"ERROR:BitGen - Bit files can only be generated for Engineering Silicon by enabling the -g es:<digit> BitGen option."
Why is this happening?
When targeting an XC3S100E device (RevA), the "-g es<digit>" option must be enabled.
The BitGen option can be enabled in ISE by following these steps:
1. In Project Navigator 7.1sp1, in the Processes for Source pane, right-click Generate Programming File.
2. Select Properties.
3. In the General Options tab of the Process Properties window, select Advanced for the Property display level.
4. Write value "-g es:1" for the Property Name Other BitGen Command Line Options.
5. Click OK.
1. The "-g es<1>" option is only needed for the first revision (rev A) of XC3S100E ES silicon. The revision is denoted in the part markings (AGQ). For more information on reading the part markings of a Xilinx device, see (Xilinx Answer 1067).
2. In 7.1.03i, you will not need to set this option when targeting an XC3S100E part, as the bitstreams generated will be for rev B silicon. However, if you are still targeting rev A silicon (AGQ), you will need to manually set this option by following the above steps.
3. If you are generating a bitstream for an XC3S500E, 7.1.03i is needed and the "-g es:<>" option does not need to be set.
This problem has been fixed in the latest 7.1i Service Pack available at:
The first service pack containing the fix is 7.1i Service Pack 3.