Aurora Solution Center
The Aurora Solution Center is a resource to help answer any questions related to the Aurora cores.
Whether implementation, board level, or any other aspect of the design process, the Solution Center aims to guide you to the correct information.
Design Assistant
Aurora Solution Center - Design Assistant
The Aurora Design Assistant walks you through the recommended design flow for Aurora 8B10B/ Aurora 64B66B designs while debugging commonly encountered issues, such as simulation issues, Initialization failures, and data errors.The Design Assistant provides useful design and troubleshooting information, but also points you to the exact documentation you need to read to help you design efficiently with Aurora 8B10B/Aurora 64B66B.
Note: This Answer Record is a part of the Xilinx Aurora Solution Center (Xilinx Answer 21263).
The Xilinx Aurora Solution Center is available to address all questions related to Aurora 8B10B/Aurora 64B66B.
Whether you are starting a new design with Aurora or troubleshooting a problem, use the Aurora Solution Center to guide you to the right information.
The Xilinx Aurora Solution Center is available to address all questions related to Aurora 8B10B/Aurora 64B66B.
Whether you are starting a new design with Aurora or troubleshooting a problem, use the Aurora Solution Center to guide you to the right information.
Please first select the design phase where you have a question or are troubleshooting an issue related to your Aurora design.
This ensures that the Aurora Design Assistant points you to the information you need to continually move forward with your design.
| (Xilinx Answer 64088) | Core Generation |
| (Xilinx Answer 64089) | Design Implementation |
| (Xilinx Answer 64090) | IPI Flow |
| (Xilinx Answer 64091) | Simulation |
| (Xilinx Answer 64092) | Hardware Debug |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 64088 | Aurora Design Assistant - Core generation | N/A | N/A |
| 64089 | Aurora Design Assistant - Design Implementation | N/A | N/A |
| 64090 | Aurora Design Assistant - IPI flow | N/A | N/A |
| 64091 | Aurora Design Assistant - Simulation | N/A | N/A |
| 64092 | Aurora Design Assistant - Hardware Debug | N/A | N/A |
Documentation
Aurora Solution Center - Documentation
This answer record contains a list of all of the documentation that is relevant to Aurora IPs.It includes user guides, data sheets, errata with transceiver-related items, application notes, and white papers.
Aurora 8B/10B:
- Aurora 8B/10B Protocol Specification
- LogiCORE IP Aurora 8B/10B Data Sheet (DS637)
- LogiCORE IP Aurora 8B/10B User Guide (UG353)
- LogiCORE IP Aurora 8B/10B Data Sheet (AXI-4 stream) (DS797)
- LogiCORE IP Aurora 8B/10B User Guide (AXI-4 stream) (UG766)
- LogiCORE IP Aurora 8B/10B Product Guide (AXI-4 stream) (PG046)
Aurora 8B/10B Bus Functional Model User Guide
Aurora 64B/66B:
- Aurora 64B/66B Protocol Specification
- LogiCORE IP Aurora 64B/66B Data Sheet (DS528)
- LogiCORE IP Aurora 64B/66B User Guide (UG237)
- LogiCORE IP Aurora 64B/66B Data Sheet (AXI-4 stream) (DS815)
- LogiCORE IP Aurora 64B/66B User Guide (AXI-4 stream) (UG775)
- LogiCORE IP Aurora 64B/66B Product Guide (AXI-4 stream) (PG074)
Aurora 8B/10B Virtex-4 FX:
- Aurora 8B/10B Protocol Specification
- Aurora 8B/10Bfor Virtex-4 FX FPGA Data Sheet (DS128)
- Aurora 8B/10Bfor Virtex-4 FX FPGA User Guide (UG061)
- Aurora 8B/10Bfor Virtex-4 FX FPGA Getting Started Guide (GSG173)
Application Notes:
Design Advisories
Design Advisory Master Answer Record for LogiCORE IP Aurora 8B10B and Aurora 64B66B
Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.For a list of all current Release Notes and Known Issues for Aurora 8B10B IP, please refer to the IP Release Notes Guide:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
Design Advisory Alerted on January 21, 2013:
| 01/21/2013 | (Xilinx Answer 53304) | Design Advisory for Aurora 8B10B v8.3 - OOB attribute settings update for 7 series GTX/GTH Transceivers and Zynq-7000 SoC Transceivers |
Design Advisory Alerted on October 28, 2013:
| 10/28/2013 | (Xilinx Answer 51554) | Design Advisory for Aurora 64B66B v8.1 or earlier - Core initialization is inconsistent on consecutive RESET and PMA_INIT inputs |
Design Advisory Alerted on August 3, 2015:
| 08/03/2015 | (Xilinx Answer 64793) | Design Advisory for Aurora 8B10B v11.0 (or) earlier - Artix-7 GTP - Simplex RX core is not de-asserting MMCM Reset and as a result RXRESETDONE is not HIGH |
Design Advisory Alerted on May 9, 2016:
| 05/09/2016 | (Xilinx Answer 66963) | Design Advisory for Aurora 8B10B v11.0 Rev2 or later - Artix-7 GTP - Channel up toggles periodically for Verilog IP |
Revision History:
| 01/21/2013 | Initial release |
| 10/28/2013 | Updated DAAR#51554 |
| 08/03/2015 | Updated DAAR#64793 |
| 05/09/2016 | Updated DAAR#66963 |