UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21445

Schematic - "ERROR:DesignEntry:20 - Pin '' is connected to a bus of a different width"

Description

When I run a process on my schematic design module, the following error occurs:

"Started process "View HDL Functional Model".

ERROR:DesignEntry:20 - Pin "<pin_name>" is connected to a bus of a different width."

Solution

Before a schematic design is implemented, it is first converted to either Verilog or VHDL (depending on the setting of the Generated Simulation Language property). As part of the conversion process, a Design Rule Check (DRC) will be run on the selected schematic and any underlying schematics. "Error: DesignEntry:20" indicates that the bit width of a symbol pin does not match the bit width of the net connected to the pin.

Example: The D input of an FD component is connected to a net named data(3:0). The pin bit width is 1 and the connected net bit width is 4.

In the ISE Schematic Editor, the pin bit width must match the bit width of the net connected to it.

To pull a specific bit (or bits) off a bus to connect it to a symbol pin of a lesser width, use name association. In the example above, the third MSB bit of data(3:0) can be used to drive the D input of the FD by connecting a net to the D input and naming it "data(2)."

If the symbol pin's bit width is greater than the width of the net that you will be connecting to it, a possible solution is:

For nets connected to input pins: Use a concatenated bus to add fill bits.

Example: A net named data(11:0) connects to the B(15:0) input of an ACC16 component. A net named "low" (connected to a GND component) could be used to pad the input data by connecting a floating net to the B(15:0) input and naming the net "low,low,low,low,data(11:0)."

For nets connected to output pins: Connect a bus net with width matching the pin width to the pin, but use just the portion of the bus that is needed.

Example: A user would like to use the two most significant bits of the Q(15:0) output of a binary counter. They connect a hanging net to the Q(15:0) output and name it cnt(15:0). The two most significant bits are then used by naming another net "cnt(15:14)."

AR# 21445
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article