We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21459

JTAG/BSCAN -The I/O is at a logic level low when sending a HIGHZ command or when disabling the output cell, why?


During JTAG/BSCAN testing, the ATE tester returns a "stuck at 0" fault on the FPGA pins. The error is generated when sending the HIGHZ command or when using EXTEST to disable the Output cell. Why?

How can an interconnection test be performed on such I/Os?


When sending the HIGH-Z command or an EXTEST to disable an output cell, a pull-down is placed on the I/O pad.

The BSDL files reflect this behavior: 2 (BC_2, IO_PAD448, output3, X, 1, 1, PULL0), "PULL0" being the Disable result.

This is necessary to guarantee a valid logic level during the tests.

For example, to test the presence of an external pull-up with a SAMPLE instruction:

If the external pull-up is here, the I/O will read a 1.

If the external pull-up is not here and the I/O is left floating (no pull-down), the level is not guaranteed.

Therefore, it is necessary to add a pull-down inside the I/O to detect a missing external pull-up.

To disable the pull-down during a JTAG/BSCAN test, configure the device with tri-state output buffers and use a back-annotated BSDL file.

For more information on generating back-annotated BSDL files, see (Xilinx Answer 15346).

AR# 21459
Date 12/15/2012
Status Active
Type General Article