When running PAR on a design targeting a Virtex-4 SX55 in a FF1148 package, I receive the following error for a global clock constrained to the master side of a GC pair in Bank 2:
"ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock IOB site The clock IOB component <clocks_1_src_clk1> is placed at site AD17. The clock IO site can use the fast path between the IO and the Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site. If this sub optimal condition is acceptable for this design you may set the environment variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this message to a WARNING and allow your design to continue."
The routed net appears to use global resources. Is this a valid error?
This invalid error occurring specifically in Bank 2 of a Virtex-4 SX55FF1148 can be bypassed by setting the environment variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING.
This problem is fixed in ISE 8.2i.
For more general information about setting ISE environment variables, see (Xilinx Answer 11630).