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AR# 23577

8.1.01 System Generator for DSP - Why does my design fail in hardware if I use the reset port on the FIFO block?

Description

Why does my design fail in hardware if I use the reset port on the FIFO block?

Solution

This is a result of a bug in System Generator for DSP 8.1.01 (8.1 Service Pack 1), where the reset port does not get created when the FIFO block is generated.

The recommendation is to use System Generator for DSP 7.1, or System Generator for DSP 8.1 (no service pack), if you need a reset on the FIFO in your design.

This has been fixed System Generator for DSP 8.2, released in August 2006.

AR# 23577
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article