My design failed during the packing stage of MAP with the following errors.
What do these errors mean and how do I correct them?
These messages usually mean that the DDR Registers were not eligible to be packed into an ILOGIC/OLOGIC component.
This is very similar to the issue of flip-flops failing to pack into I/O components.
However, DDR Registers do not have the alternative of packing into a Slice component, resulting in an error.
Possible causes for the packing failure include:
For this last case, the error may occur when a synthesis fanout limit has been applied to a reset line resulting in the reset line being partitioned into separate but logically equivalent nets, and the synthesizer fails to group the FF loads properly.
n this case, the following work-arounds are available: