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AR# 24280

LogiCORE XAUI - Verilog example design wrapper files contain XST-specific synthesis constraints that are not read by Synplify and other third party synthesis tools

Description

The XAUI example design wrapper files are only tested with XST; they are not tested with Synplify or other third party synthesis tools. The XAUI Verilog example design wrapper files contains XST-specific synthesis constraints that are not read by Synplify and other third party synthesis tools.

In v6.2 and earlier, Virtex-4 GT11 attributes are not picked up by third party synthesis tools, which results in the MGT not functioning correctly in hardware. When generating for Virtex-2 Pro, Virtex-5, or Virtex-4 in v7.0 or later of the core, the constraints are only for timing simulation and do not affect behavior in hardware, do not affect the VHDL example design wrapper files. A description of the synthesis constraints are listed below.

Solution

In XAUI v6.2 and earlier Virtex-4 GT11 attributes are passed with XST-specific synthesis constraints:

// synthesis attribute

Other synthesis tools (specifically Synplify) cannot pick up these constraints. There are actually defparam attributes for simulation that are currently provided, but they have the following around these attributes and, as a result, synthesis tools do not pick up these defparams:

// synopsys translate_off

// synopsys translate_on

The deletion of all of the translate_off and translate_on lines allow synthesis tools to read in these defparams; they are located in the following two files:

- Transceivers.v: there are four sets around the defparams for each of the GT11s.

- Xaui_v6_2_top.v: they are placed around the defparams:

defparam gt11clk_mgt_i.SYNCLK1OUTEN = "ENABLE";

defparam gt11clk_mgt_i.SYNCLK2OUTEN = "DISABLE";

In XAUI v7.0 and later, the translate_off and translate_on synthesis directives are removed from the example design wrapper files and this is no longer a problem.

The example design wrappers for Virtex II-Pro, Virtex-4, and Virtex-5 contain ASYNC_REG constraints that are only picked up by XST. This constraint only affects timing simulation; it disables "X" propagation during timing simulation. In the event of a timing violation, the previous value is retained on the output instead of becoming unknown. These constraints can be moved to the UCF if a synthesis tool other than XST is used.

AR# 24280
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article