We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24729

9.1i GTP SmartModel timing simulation - Incorrect data on TXN/TXP outputs in Modelsim VHDL/Verilog simulation


Incorrect data is seen at the TXN/TXP output of the GTP_DUAL when running VHDL or Verilog timing simulation in Modelsim with the 9.1i libraries and earlier.


The GTP_DUAL has a large clock insertion delay. The input data gets to the internal flops much faster than the clock does. This causes the negative Setup delay which can be seen in Timing Analyzer or annotated in the SDF file. A negative Setup value means that the data is allowed to arrive at a flop *after* the clock edge has arrived. Any data that arrives no later than the negative Setup delay is still valid data.

In Modelsim, however, when the data changes after the clock edge but before the setup time, the incorrect data is registered internally. This incorrect data is the data that is present at the time of the clock edge. If there is enough timing margin that the data changes before the rising edge of the userclk, the simulation will work correctly.

This problem is seen only in Modelsim. NCSIM and VCS simulations are not affected. This has been fixed with the 9.2.03i libraries and later.

AR# 24729
Date 12/15/2012
Status Active
Type General Article