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AR# 25406

MIG v1.73 - Release Notes and Known Issues for 9.2i IP Update 1 (9.2i_IP1)

Description

This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v1.73 released in 9.2i IP Update 1, and contains the following information:

- General Information

- Software Requirements

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 25222).

Solution

General Information

- MIG is no longer provided as a separate download, but is now incorporated into IP Updates. MIG v1.73 is available through 9.2i IP Update 1. MIG v1.73 is the MIG v1.7 release brought into the IP Update with added Spartan-3A DSP support and a few bug fixes which are noted below.

Software Requirements

- ISE 9.2.01i

- Windows XP (32 bit)

MIG v1.73 New Features

- DDR and DDR2 SDRAM support for Spartan-3A DSP

MIG v1.7 New Features

General New Features and Changes

- Supports "Create New Memory Part" for all the designs.

- DDR and DDR2 SDRAM designs for Spartan-3A.

- DDR SDRAM is supported for Virtex-5.

- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM.

- MIG now pops up the design notes specific to the generated design.

- Supports pin-out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs.

- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes.

- Supports differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2.

- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A.

- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST".

- Default setting "DCI for Address and Control " is changed to "unChecked".

- Frequency slider is changed to editable box in the GUI.

- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names.

- Removed console window when running MIG through CORE Generator.

- WASSO table (Set Advanced Options) accepts only numeric characters.

- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32.

- Provided web links for all Application Notes in the documents folder of the designs.

- Provided link to Data Sheet instead of Log Sheet in the output window.

- Support of Constraint "CONFIG PROHIBIT" while reading the UCF in the reserve pins window.

- WASSO limits the number of pins to be used in a bank per controller. For example, in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank.

- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition.

Virtex-5 New Features and Changes

DDR2 SDRAM

- New controller with several high-performance features. All the features are described in detail in the Application Notes.

- Enhanced data calibration algorithms for higher reliability.

- Bank Management feature is supported.

- Supports VHDL.

- The user is no longer required to set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear.

- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User Guide for a definition of the User I/F bus.

- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin-outs will be different between MIG1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to all the memory interface signals.

c. Signals such as "Error" outputs are not part of the WASSO count.

DDR SDRAM

- This is a new design for MIG. Supports Verilog and VHDL.

- Bank Management feature is supported.

- The user is no longer required to set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear.

QDRII SRAM

- Added support for VHDL.

- Added support for 72-bit designs.

- Added first level of calibration. This includes a dummy write of 1s and 0s to the memory. This pattern helps to calibrate for the CQ/Q delay.

- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6

- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons.

- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin-outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to the output signals only.

Virtex-4 New Features and Changes

DDR2 SDRAM Direct Clocking

- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design.

- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins.

- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.

- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options.

- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers.

- Removed all TIGs in UCF. The reset signal is now registered in every module.

- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.

- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.

- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.

- Replaced `defines with localparams for Verilog.

- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.

- Several state machines now use "One-Hot Encoding".

- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.

- Signal INIT_DONE is brought to top module.

- Removed the UniSim primitive components declaration from VHDL modules.

- All multiples of 8-bit data widths even for x16 memory devices are now supported.

- Memory devices of speed grades -3 and -667 are now supported.

- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin-outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to all the memory interface signals.

c. Signals such as "Error" outputs are not part of the WASSO count.

DDR2 SDRAM SERDES Clocking

- Implemented a new calibration scheme. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the Application Note.

- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.

- Support for ODT.

- DQS# Enable is selectable from GUI through Mode registers.

- Removed all TIGs in UCF. The reset signal is now registered in every module.

- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.

- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.

- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.

- Replaced `defines with localparams for Verilog.

- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.

- Removed the UniSim primitive components declaration from VHDL modules.

- We now support all multiples of 8-bit data widths even for x16 memory devices.

- Signal INIT_COMPLETE is brought to top module.

- Memory devices of speed grades -5E and -40E are now supported.

- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin-outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to all the memory interface signals.

c. Signals such as "Error" outputs are not part of the WASSO count.

DDR SDRAM

- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.

- Removed all TIGs in UCF. The reset signal is now registered in every module.

- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.

- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.

- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.

- Replaced `defines with localparams for Verilog.

- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.

- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.

- Removed the UniSim primitive components declaration from VHDL modules.

- We now support all multiples of 8-bit data widths even for x16 memory devices.

- The signal "init_done" is now a port in the top module.

- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin-outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to all the memory interface signals.

c. Signals such as "Error" outputs are not part of the WASSO count.

RLDRAM II

- There is a new option for the user to select the reset polarity, this option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.

- Removed all TIGs in UCF. The reset signal is now registered in every module.

- The design now uses CLK0, instead of CLK50 and div16clk.

- CLK200 is changed to differential clocks in mem_interface_top module (Design top).

- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal.

- Removed unused parameters from the parameter file.

- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.

- Replaced `defines with localparams for Verilog.

- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.

- Removed the UniSim primitive components declaration from VHDL modules.

- The signal "INIT_DONE" is now a port in the top module.

- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8.

- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets.

- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file.

- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin-outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO count is applied on output signals only for SIO memory types.

c. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool.

QDRII SRAM

- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.

- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic.

- Supports generation of designs without DCM.

- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC.

- Removed all TIGs in UCF. The reset signal is now registered in every module.

- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.

- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.

- Replaced `defines with localparams for Verilog.

- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.

- Removed the UniSim primitive components declaration from VHDL modules.

- The signal "DLY_CAL_DONE" is now a port in the top module.

- The I/O Standard generated for system signals are LVCMOS18. Users can change this as applicable.

- Added support for DDR Byte writes.

- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin-outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to the output signals only.

c. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool.

DDRII SRAM

- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.

- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic.

- Supports generation of designs without DCM.

- Part CY7C1526V18-250BZC has been removed from Memory Parts list.

- Removed all TIGs in UCF. The reset signal is now registered in every module.

- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.

- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.

- Replaced `defines with localparams for Verilog.

- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.

- Removed the UniSim primitive components declaration from VHDL modules.

- The signal "DLY_CAL_DONE" is now a port in the top module.

- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.

- Added support for DDR Byte writes.

- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin-outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to all the memory interface signals.

c. Signals such as "Error" outputs are included in WASSO count.

Spartan-3, Spartan-3E, Spartan-3A New Features and Changes

- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.

- Removed all TIGs in UCF. The reset signal is now registered in every module.

- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.

- Replaced `defines with localparams for Verilog.

- Removed the UniSim primitive components declaration from VHDL modules.

- We now support all multiples of 8-bit data widths even for x16 and x4 memory devices.

- The signal "cntrl0_data_valid_out" is now a port in the top module.

- DQS# Enable, burst type and ODT can be selected from the MIG GUI through the Mode registers.

- Board files for Spartan-3E starter kit provided in VHDL and Verilog.

- Implemented several changes to the controller to improve timing.

- Changed the Spartan-3/3E pin allocation rule for increased efficiency. The previous rule was that DQs corresponding to a particular DQS could be within 5 tiles above and 5 tiles below the DQS. Now, the DQs can be 5 tiles above and 6 tiles below the DQS.

- Support for Spartan-3A.

Bug Fixes

Bug Fixes for MIG v1.73

- CR 439543: Virtex-5 DDR2 interface - stage 1 calibration might not find optimal calibration point. Please see (Xilinx Answer 25232) for further information regarding this issue.

- CR 442726: Twr violations occur in DDR/DDR2 SDRAM Virtex-5 designs when Address FIFO is empty and there is an Auto Refresh request. Please see (Xilinx Answer 25436) for further information regarding this issue.

- When simulating the Virtex-5 DDR2 SDRAM controller with the MULTI_BANK_EN parameter enabled, the simulation does not show up to 4 banks opened at a time. It continually shows precharges and behaves as though it does not support bank management. Please see (Xilinx Answer 25261) for further information regarding this issue.

- Modified the "component_name_cal_ctl_0.v/vhd module/entity in all Spartan designs to include a second edge detection at 200Mhz. This was missing in previous releases. The "enb_trans_two_dtct" flag is now set when "phase_cnt" is equal to 1. Previously, the flag was not set until "phase_cnt" equaled 3.

- In all Spartan designs, the cal_ctl UCF area group constraints have been moved closer to the DCM and BUFG placements. This minimizes the net delay in the clock to LUT delay chain.

Bug Fixes for MIG v1.72

- See (Xilinx Answer 25056)

Known Issues

- Please see (Xilinx Answer 24979) for general CORE Generator support items.

- Please see (Xilinx Answer 24432) for information on mapping the user interface address to account for the auto-precharge bit A10 for Virtex-4 DDR/DDR2 SDRAM controllers and general information on mapping the user interface address for Virtex-5 DDR/DDR2 SDRAM controllers.

- Spartan-3/-3E/-3A x4 designs are only supported for data widths up to 72-bits. Wider interfaces implement with incorrect local clock routes when top/bottom banks are selected. This issue is observed only for x4 memory component and for top/bottom banks. This will be fixed in MIG 2.0.

- In Spartan-3/-3E/-3A designs, users can select "Write Pipe Stages" from "Set Advanced Options." The default value of "Write Pipe Stages" is 4. If any other value (3,2,1,0) is selected, the test_bench module should include the extra pipe stages on the write data and data mask signals. This is missing in the design. There is no issue for the default Write Pipe Stage of 4. This will be fixed in MIG 2.0.

- Please see (Xilinx Answer 24964) for information on the "Verify My UCF" option in the MIG GUI.

- You should be aware of the stepping level of your target Spartan-3 devices and how this affects the maximum frequency achievable for the memory component that is generated. The MIG tool does not adjust the frequency for any particular stepping level in use. Please consult the relevant device data sheets or errata for more information on stepping. These documents are located at:

http://www.xilinx.com/support/library.htm.

AR# 25406
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article