How do system_reset and link_rest work?
In Xilinx SRIO example design, rio_reset.v is provided to handle link reset. It issues a lnk_linkreset_n when a system reset occurs. This causes the SRIO PHY to send four link reset control symbols to the connected device forcing it to reset. Once this link goes down, a system reset is then issued to the SRIO PHY. This reset sequence is necessary to prevent ackIDs from getting out of sync.
Indicates that the core has received four reset device control symbols from the linked device and PHY is going through the reset. This output should be used to reset the PHY side of the buffer to avoid misalignment of AckID.
Asserting sys_reset_n causes a hard reset of the entire core. The initial hard reset should be generated by the user as part of the startup sequence and subsequently as needed by the lnk_reset_n. Special care must be used when resetting the RapidIO device. Both link partners (devices) should be reset to guarantee AckID alignment.