The MIG Virtex-5 FPGA dual-rank design limits the maximum frequency to 150 MHz mainly because the physical layer of the design calibrates only on one rank and due to the wide range of loading. Theoretically, there can be significant differences in timing between the ranks even on a single SO-DIMM. Also, because dual rank can come in many configurations, such as registered or unregistered, the loading on the address and control can vary significantly. For these reasons, MIG sets the maximum frequency to 150 MHz.It is possible to push this frequency limit by careful consideration of the following:
1. Memory type and vendor.
- How closely is the timing matched between the ranks? Major memory/DIMM vendors might have characterization data available.
- How heavily loaded are the address and control? RDIMM substantially reduces the loading on the address and control.
2. Thorough SI Simulation using IBIS and timing budget analysis.
- Carefully analyze the loading effects.
3. If necessary (after considering 1 and 2 above), implement logic to calibrate on each rank and average, or change the calibration on the fly.
- It is important to know that dynamic adjustments might affect latency as there is only an up/down signal for the IDELAY and not a parallel load.
- Logic would also need to be added or changed in order to make the calibration dynamic. The current calibration logic selects positive or negative edges during calibration.
The Virtex-5 FPGA design uses top-level HDL parameters to easily parameterize the design. To change the operating frequency within the MIG design, modify the CLK_PERIOD top-level parameter in the "ddr2_sdram.v/.vhd" file.
Note: Xilinx only supports operation of dual-rank designs up to 150 MHz. Full verification and implementation of increasing this frequency are the sole responsibility of the user.