We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32020

10.1 EDK - Processor hangs when accessing non-existing register address


When I generate a pcore in the Create / Import Peripheral (CIP) Wizard with 3 registers, there is a wrong number for C_ARD_NUM_CE_ARRAY:

Analyzing hierarchy for entity <user_logic>: C_NUM_REG = 3

Analyzing hierarchy for entity <plbv46_slave_single>:


reading baseaddress..

C_BASEADDR + 0x0 ok

C_BASEADDR + 0x4 ok

C_BASEADDR + 0x8 ok


MicroBlaze stalls when reading the 4th (non-existent) register.

However, when I make a pcore with 2 registers, ce_array is correct:

Analyzing hierarchy for entity <user_logic>: C_NUM_REG = 2

Analyzing hierarchy for entity <plbv46_slave_single>: C_ARD_NUM_CE_ARRAY = (2)


There is no register that exists at that address space, therefore, the C_INCLUDE_DPHASE_TIMER parameter needs to be set to 1 to allow data phase timeout. This parameter can be set either in the MHS or the MPD file. More information about this parameter can be found in the IPIF data sheet.

AR# 32020
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked