UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32475

MIG v3.0, Spartan-3 FPGA DDR/DDR2 - Known Issues with Verify UCF and Update Design

Description

The MIG v3.0 Verify UCF and Update Design features are intended to provide users with the ability to verify changes to a UCF, and update a design with an older version of a MIG design or a modified UCF.

A number of known issues with these features in MIG v3.0 are detailed in this answer record.

Solution

Issues with Update Design 

1)  Update Design does not flag errors when an input UCF only contains I/O LOCs. 

Update Design completes, but the output design does not include the appropriate constraints and might fail during MAP with an error similar to the following: 

ERROR:Pack:679 - Unable to obey design constraints (LOC=SLICE_X30Y56) which require the combination of the following symbols into a single SLICEM component: 

NOTE: The design might complete implementation, but does not use the desired routing and could cause issues in hardware. 

To work around this issue, the UCF input in Update Design must include one CORRECT set of SLICE constraints associated with a DQ bit. \

 
The following is an example of a set of DQ SLICE constraints: 

NET "cntrl0_ddr2_dq[0]" LOC = "B21"; #bank 1 
INST "main_00/top0/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit0" LOC = SLICE_X62Y90; 
INST "main_00/top0/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit0" LOC = SLICE_X62Y91; 

To determine the correct SLICE constraints, see (Xilinx Answer 32449)

If a correct set of SLICE constraints is included in the input UCF, Update Design properly verifies the I/O LOCs and outputs an accurate design with all required constraints associated with the input UCF.

 

2)  Update Design does not issue a warning or error if the placement rules for rst_dqs_div_in and rst_dqs_div_out are violated. 

For details on the placement rules for rst_dqs_div_in and rst_dqs_div_out, see (Xilinx Answer 32449)

Manually verify that these rules are followed. 

Correct placement of these signals is required to ensure proper data capture. 

 

Issues with Verify UCF

1)  When only I/O LOCs reside in the input UCF, Verify UCF completes successfully even if the input UCF violates design pin allocation rules. 

To force Verify UCF to properly analyze the UCF, it must include all appropriate constraints.

This means all of the constraints included in the UCF output by MIG must be properly set in the UCF input to Verify UCF.  

For a complete list of Spartan-3 FPGA DDR/DDR2 pin allocation rules, see (Xilinx Answer 32449).  

 

2)  Verify UCF does not issue a warning or error if the placement rules for rst_dqs_div_in and rst_dqs_div_out are violated. 

For details on the placement rules for rst_dqs_div_in and rst_dqs_div_out, see (Xilinx Answer 32449)

Manually verify that these rules are followed. 

Correct placement of these signals is required to ensure proper data capture. 

These issues are resolved in MIG v3.1.

AR# 32475
Date Created 04/10/2009
Last Updated 08/29/2014
Status Active
Type General Article
Devices
  • Spartan-3
  • Spartan-3A
  • Spartan-3A DSP
  • More
  • Spartan-3AN
  • Spartan-3E
  • Less
IP
  • MIG