UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33343

11.1 BitGen - "ERROR:Bitgen - Incorrect DCI setting for bank 21. It cannot be used as master."

Description

When using DCI cascading in a Virtex-5 or Virtex-6 device, the following error occurs:

"ERROR:Bitgen - Incorrect DCI setting for bank 21. It cannot be used as master.

ERROR:Bitgen:157 - Bitgen will terminate because of the above errors."

How do I resolve this error?

Solution

This error is caused by a limitation of the software implementation of DCI cascading. The software currently requires that the bank used as the master DCI bank must have an input with a compatible DCI IOSTANDARD that is being used in the slave bank.

To work around this issue, create a dummy input with a compatible DCI IOSTANDARD that is being used in the slave DCI bank. It is not necessary that the input is connected to the board or the internal fabric design.

More information on DCI Cascading can be found in the Virtex-5 FPGA User Guide:

http://www.xilinx.com/support/documentation/user_guides/ug190.pdf

This restriction is planned to be removed starting with BitGen 11.4.

AR# 33343
Date Created 09/02/2009
Last Updated 12/15/2012
Status Active
Type General Article