The MIG v3.2 Virtex-6 DDR2/DDR3 design fails during BitGen if Data Mask is disabled in MIG generation.
The following errors are displayed:
ERROR:PhysDesignRules:9 - The network <clk_wr_i> is only partially routed.
ERROR:PhysDesignRules:9 - The network <clk_wr_o> is only partially routed.
ERROR:PhysDesignRules:796 - Component u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm[2].u_phy_dm_iob/gen_dm_oserdes_ddr2.u_oserdes_dm has routethru conflicts.