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AR# 33405

MIG v3.2 Virtex-6 FPGA DDR2/DDR3 - When data mask is disabled, BitGen fails with PhysDesignRules errors


The MIG v3.2 Virtex-6 DDR2/DDR3 design fails during BitGen if Data Mask is disabled in MIG generation. 

The following errors are displayed:

ERROR:PhysDesignRules:9 - The network <clk_wr_i> is only partially routed. 

ERROR:PhysDesignRules:9 - The network <clk_wr_o> is only partially routed. 

ERROR:PhysDesignRules:796 - Component u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm[2].u_phy_dm_iob/gen_dm_oserdes_ddr2.u_oserdes_dm has routethru conflicts.


These errors occur because the RTL incorrectly includes the data mask logic regardless of whether the option is enabled or disabled in the MIG GUI.

To work around this issue, comment out the instantiation of the phy_dm_iob module in the phy_data_io module.

This issue is resolved in MIG v3.3, released with ISE Design Suite 11.4.
AR# 33405
Date 08/14/2014
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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  • Virtex-6 LXT
  • Virtex-6 SXT
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  • MIG
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