MIG v3.2 Virtex-6 FPGA DDR3 designs that target x8 devices with a 72-bit data width fail during MAP if the Address/Control and System Control are in the same FPGA bank. Errors similar to the following occur:
"ERROR:Place:899 - The following IOBs use the Digitally Controlled Impedance feature (DCI) and have been locked (LOC constraint) to the I/O bank 33. This feature requires the VRN and VRP pins within the same I/O bank to be connected to reference resistors. The following VR pins are currently locked and can't be used to supply the necessary reference.
IO Standard: Name = DIFF_SSTL15_T_DCI, VREF = NR, VCCO = 1.50, TERM = SPLIT,
DIR = BIDIR, DRIVE_STR = NR
List of locked IOB's:
List of occupied VR Sites:
VR site IOB_X2Y55 is occupied by comp phy_init_done"
The only way to work around this error is to regenerate the MIG design with the Address/Control and System Control in different FPGA banks.
The issue is due to the System Control group which includes the phy_init_done, sys_rst, and error signals. Note that in most user designs, these signals are not pulled out to I/O, so selecting a different bank for this group and leaving the Address/Control in the desired FPGA bank is not a concern.