AR# 33469

Virtex 6 FPGA GTX Transceiver Wizard v1.3 - Release Notes and Known Issues


This Answer Record contains the release notes and an updated known issues list for the Virtex-6 FPGA GTX Transceiver Wizard.



For the most recent updates to the IP installation instructions for this core,

please go to:

For system requirements:

This file contains release notes for the Xilinx Virtex-6 FPGA GTX Transceiver Wizard v1.3. For the latest core updates, see the product page at:


- Virtex-6 lower power device addition

- Virtex-6 HXT device addition

- Enhanced clocking graphics addition to GUI


- Fixed CR 524875, 524454, 524029


The following are known issues for v1.3 of this core at time of release:

- Virtex-6 FPGA solutions are pending hardware validation

- This version of the Wizard has limited support for the larger devices with 36 transceivers. The Wizard will only display the lower 24 transceivers on the transceiver selection page.

- To work on around this issue

1. Select transceivers from the available list.

2. Generate the desired wrapper.

3. Manually modify the ucf file to place the transceivers

where desired.

- While selecting left column, the starting transceiver location for XC6VHX380T-FF1923 and XC6VHX565T-FF1923 devices appears to be X0Y8.

- CR Number 531254

- To work on around this issue

1. Generate the design with start transceiver location as X0Y8

2. In the generated ucf file,modify transceiver location to desired

value allowed in the selected device

3. Synthesize the design

- Setup and hold time error is observed in designs that use multiple GTX and different reference clock sources.

- CR Number 524285 and 527558.

The most recent information, including known issues, workarounds, and resolutions for this version is provided in the release notes Answer Record for the ISE 11.3 IP Update at:


To obtain technical support, create a WebCase at Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.


Date By Version Description


09/16/2009 Xilinx, Inc. 1.3 11.3 Release

06/24/2009 Xilinx, Inc. 1.2 11.2 Release

04/24/2009 Xilinx, Inc. 1.1 Initial release


Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33475 Virtex-6 FPGA GTX Transceiver - Known Issues and Answer Record List N/A N/A
AR# 33469
Date 12/15/2012
Status Active
Type General Article