The ChipScope tool VIO Example Design that is generated with v5.4 of the Serial RapidIO Endpoint Solution has several problems, including the following:
The following are updated ZIP files that resolve the issues for both Verilog or VHDL generated example designs using 8-bit Device IDs.
Follow the instructions in the README files to install the update.
If you are using a 16-bit Device ID and require the updated files, please contact Xilinx Technical Support and reference this Answer Record.
The Verilog and VHDL patches are attached to this Answer Record.
These updated files are to be included in the v5.5 release of the Serial RapidIO Core.