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AR# 34107

11.4 EDK - MMCM divide parameter and its effect on Clock Generator

Description

Certain combinations of the MMCM counter settings, phase shift, and all settings of the variable fine phase shift might cause the CLKOUTn phase shift to show up incorrectly in hardware. This is documented in (Xilinx Answer 33849). This specifically affects Virtex-6 FPGA Clock_Generator designs which use a CLKFBOUT_MULT_F value of 4. Clock_Generator uses the CLKFBOUT_MULT_F parameter to ensure the internal VCO frequency of the MMCM to the highest possible setting according to the FPGA speed grade. Having a higher VCO frequency reduces jitter on the output clocks. This setting of 4 will be generated by Clock_Generator in certain combinations of high-level parameter settings. For example, the input clock of a Clock_Generator has the following frequencies:

FPGA Speed Grade

From (MHz)

To (MHz)

-1

240

300

-2

288

360

-3

320

400

The ISE 11.4 tools will not generate an error and issues will be seen in hardware. In ISE 11.4.1 design tools, a DRC error will be generated.

Solution

To work around this issue, users need to manually modify the MMCM parameters using the Clock_Generator low-level parameters to ensure the CLKFBOUT_MULT_F parameter is not set to 4 for any of the MMCM, and, meanwhile, the VCO frequency and MMCM parameter values remain valid according to the Virtex-6 FPGA Clocking Resources (Xilinx UG362).

Workaround steps:

Step 1: Identify if CLKFBOUT_MULT_F = 4 is set to MMCM generated by Clock_Generator

- Open the design in XPS

- Right click on the Clock Generator peripheral and select "Configure IP"

- Bring forward the "Low-level Parameters" tab

- Check the "Insert low-level parameters in MHS file" box

- Hit the OK button

- Open the MHS file and search for the parameter C_MMCMn_CLKFBOUT_MULT_F(n = 0,..., 3) within the clock_generator instance

- If the value is equal to 4, then continue on to Step 2 otherwise you are done

Step 2: Manually modify the CLKFBOUT_MULT_F value in MHS file

- When manual modification is required, find the following parameter in the Clock_Generator instance:

PARAMETER C_MMCMn_CLKFBOUT_MULT_F = 4.0

PARAMETER C_MMCMn_DIVCLK_DIVIDE = 2

PARAMETER C_MMCMn_CLKOUT0_DIVIDE_F = 2.0

PARAMETER C_MMCMn_CLKOUTm_DIVIDE = 2

Where n = 0, , 3 and m = 1, , 6. And modify the parameters to ensure the M to D and DO relationship is maintained. For the example, this would be:

PARAMETER C_MMCMn_CLKFBOUT_MULT_F = 8.0

PARAMETER C_MMCMn_DIVCLK_DIVIDE = 4

PARAMETER C_MMCMn_CLKOUT0_DIVIDE_F = 2.0

PARAMETER C_MMCMn_CLKOUTm_DIVIDE = 2

Step 3: Manually modify the C_CLK_GEN value in MHS file

- When manual modification is required, find the following parameter in the Clock_Generator instance:

PARAMETER C_CLK_GEN = UPDATE

Either its value is set to UPDATE, or it is not specified in the MHS file, manually change its value to PASSED.

PARAMETER C_CLK_GEN = PASSED

This prevents the XPS flow from overwriting the manually modified Clock_Generator low-level parameter values.

- Save and close the MHS file

DO NOT open Clock_Generator configuration dialog in the XPS any more after manually changing the Clock_Generator low-level parameter value. The dialog always overwrites the Clock_Generator low-level parameter values automatically.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34019 ISE Design Suite 11.4.1 - Known Issues for Virtex-6 FPGA Service Pack N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34019 ISE Design Suite 11.4.1 - Known Issues for Virtex-6 FPGA Service Pack N/A N/A
AR# 34107
Date Created 01/13/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
Tools
  • ISE Design Suite - 11.4
  • EDK - 11.4
IP
  • Clock Generator