AR# 34348

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14.x Timing Constraints - How can I exclude cross-domain paths from Timing Analysis?

Description

If I apply a PERIOD constraint to the input clock of DCM/PLL/MMCM, the constraints are automatically propagated to the output clocks. While these clocks are considered as related clocks and the cross-domain timing paths are analyzed by Timing Analyzer, how can I exclude cross-domain paths from Timing Analysis?

Solution

Solution 1

To remove a set of paths from timing analysis, if you are sure that these paths do not affect timing performance (False paths), use the FROM-TO constraint with the timing ignore (TIG) keyword. To specify the timing ignore (TIG) constraint for this method, define the following:

  • A set of registers for the source time group
  • A set of registers for the destination time group
  • A FROM-TO constraint with a TIG keyword to remove the paths between the groups

Following is an example of the DCM/PLL/MMCM usage; suppose clk_in is the input clock of DCM/PLL/MMCM and clk_0, clk_90, clk_180 are the output clocks:

net "clk_in" TNM_NET = clk_in_grp;
net "clk_0" TNM_NET = clk0_grp;
net "clk_90" TNM_NET = clk90_grp;
net "clk_180" TNM_NET = clk180_grp;
TIMESPEC TS_clk_in = PERIOD "clk_in_grp" 10ns HIGH;

1. Assuming signal clk_in drives synchronous elements beyond the DCM/PLL/MMCM

TIMEGRP "clk_out_grp" = "clk0_grp" "clk90_grp" "clk180_grp";
TIMESPEC TS_01 = FROM "clk_in_grp" TO "clk_out_grp" TIG;
TIMESPEC TS_02 = FROM "clk_out_grp" TO "clk_in_grp" TIG;

These constraints ignore the cross-domain paths between the input clock and the output clocks of the DCM/PLL/MMCM.

2. Assuming signal ckl_in only drives the DCM/PLL/MMCM

TIMESPEC TS_01 = FROM "clk0_grp" TO "clk90_grp" TIG;
TIMESPEC TS_02 = FROM "clk0_grp" TO "clk180_grp" TIG;
TIMESPEC TS_03 = FROM "clk90_grp" TO "clk0_grp" TIG;
TIMESPEC TS_04 = FROM "clk90_grp" TO "clk180_grp" TIG;
TIMESPEC TS_05 = FROM "clk180_grp" TO "clk0_grp" TIG;
TIMESPEC TS_06 = FROM "clk180_grp" TO "clk90_grp" TIG;

These constraints ignore the cross-domain paths among all the output clocks of DCM/PLL/MMCM.

Please refer to the Timing Constraints User Guide (UG612) for more detailed information on False paths constraints:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ug612.pdf

Solution 2

You can also add non-related PERIOD constraints for theDCM/PLL/MMCM output clocks manually in UCF instead ofautomatic propagation. The tool will not analyze the cross-domain paths as long as they are not applied related PERIOD constraints. See the following example.

Automatic propagation:

net "clk_in" TNM_NET = clk_in_grp;
TIMESPEC TS_clk_in = PERIOD "clk_in_grp" 10ns HIGH;
TIMESPEC TS_clk0 = PERIOD "clk0" TS_clk_in HIGH; (Note 1)
TIMESPEC TS_clk90 = PERIOD "clk90" TS_clk_in PHASE + 2.5 ns HIGH; (Note 1)
TIMESPEC TS_clk180 = PERIOD "clk180" TS_clk_in PHASE + 5 ns HIGH; (note 1)

Note 1: These constraints are automatically propagated to the output clocks.

Add non-related PERIOD constraints manually:

TIMESPEC TS_clk0 = PERIOD "clk0" 10 ns HIGH;
TIMESPEC TS_clk90 = PERIOD "clk90" 10 ns HIGH;
TIMESPEC TS_clk180 = PERIOD "clk180" 10 ns HIGH;

Please refer to the Timing Constraints User Guide (UG612) for more detailed information on "related" PERIOD constraints:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ug612.pdf

AR# 34348
Date 12/15/2012
Status Active
Type General Article
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