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AR# 34644

NGDBuild - ERROR:NGDBuild:770 - and on net are lined up in series.


NGDBuild - ERROR:NGDBuild:770 - <buffer_type> <buffer_name> and <buffer_type> <buffer_name> on net <net_name> are lined up in series.

This ERROR is issued when the NGDBuild DRC checks detect that multiple buffers of the same type are connected in series within your design.

Connecting buffers of the same type in series is not a valid construct for Xilinx FPGAs.


Solution 1:

In most scenarios, this has happened by accident because the offending buffers exist at different levels of hierarchy in the design.

Please review your design and ensure that your design only contains one input or output buffer for the net in question.

Be aware that this can occur when using certain IP cores such as DCM and MIG cores (which can be configured to include I/O buffers in their netlists).

Solution 2:
In some scenarios, the series buffers can be a result of the synthesis tools not properly parsing connectivity of the net in question and then automatically inserting an input or output buffer where it is not needed.

Review the synthesis report for your design for messages related to this signal path for more information.
Solution 3:
This error can occur when attempting to source BUFGs in CPLDs with internal logic.

BUFGs on CPLD devices can only be sourced by clock-capable input pins (GCLK).

AR# 34644
Date 03/24/2015
Status Active
Type Error Message
  • ISE