We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 3518

CPLD: 9500: What are the differences between reset lines in simulation and on the device


Urgency: Standard

General Description:

What is the difference between the simulation signals

PRLD/MRESET and the signals used by the global buffers GTS

and GSR?


PRLD is simply a simulation signal only. During

configuration and power-up all flip flops in the device

are set to a known level, regardless of what the user does.

However, most timing simulators are unable to simulate this

behavior, thus PRLD must be used to initialize all

flip flops in the simulation.

For more details about PRLD see (Xilinx Solution 1045).

The GTS and GSR are global buffers that route to either

all Tri-state enables or all Set/Reset pins on flip flops


To simulate these signals in a simulation, stimulus must be

put on the net names.

The GTS and GSR buffers must be routed on schematic or

inferred in your HDL code to be used, unlike the GSR signal

found in Xilinx FPGAs.

AR# 3518
Date 12/15/2012
Status Active
Type General Article