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AR# 35988

10.1/11.x MAP - BitGen issues "PhysDesignRules:1385 - Dangling pins on block..." in a design with ChipScope Pro cores

Description

BitGen issues an error similar to the following in a design with ChipScope Pro cores:

PhysDesignRules:1385 - Dangling pins on
   block:<app/PIO_interface/PIO_EP_ins/EP_MEM/i_ila_128/U0/I_NO_D.U_ILA/I_DQ.U_D
   QQ/DLY_9.DLY_9_GEN[109].I_SRLT_NE_0.DLY9/SRL16E>:<SLICEM_A6LUT>
   .  For RAMMODE programming set with DPRAM32 or SPRAM32 or SRL16 the DI2 input
   pin must be connected.

How can I resolve this issue?

Note: This article is only applicable when the block name in the error message is related to the ChipScope Pro cores.

Solution

This error occurs because MAP trims the sourceless signal which is connected to the ChipScope Pro cores.

Solution 1

If you are using a ChipScope Pro Core Generator flow, check the MAP report to see if there are messages similar to the following:

The signal "app/PIO_interface/PIO_EP_ins/EP_MEM/i_ila_128/TRIG0<108>" is sourceless and has been removed.


This indicates that the signal connected to a trigger port is sourceless and removed.

Try to remove that trigger port connection or find out why the signal is sourceless and fix the problem.

Solution 2

If you are using ChipScope Pro Core Inserter flow, check the PAR report to see if there are warnings about some nets that are undriven. 

Then use the MAP report to track the nets back to see why they were undriven and try putting an S (Save Net Flag) constraint on the nets so that it will not be trimmed.

AR# 35988
Date Created 06/02/2010
Last Updated 12/01/2014
Status Active
Type Error Message
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
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