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AR# 36104

MIG Virtex-6 DDR2/DDR3 - How to properly terminate ODT, CKE, and RESET

Description

The Memory Controller drives the ODT, CKE, and RESET signals during normal operation and LOW during initialization.

However, a pull-down with a 4.7 kOhm resistor connected to GND is still required to adhere to the DDR2 and DDR3 Memory Standards.

Note: This Answer Record is a part of the Xilinx MIG Solution Center(Xilinx Answer 34243).

The Xilinx MIG Solution Center is available to address all questions related to MIG.

Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Based off of the Power-Up Initialization Sequence defined by the DDR3 Spec, RESET# is recommended to be Low right at power On.

To guarantee this occurs while the FPGA is being configured (before it can drive RESET "Low"), the pull-down to GND is recommended.


Based off the Power-Up Initialization Sequence defined by the DDR2 Spec, CKE and ODT are supposed to be maintained at a LOW state while applying power.

To guarantee this occurs while the FPGA is being configured (before it can drive CKE and ODT "Low") we require the pull-down to GND.

Revision History
2/17/2011 - Initial Release
5/22/2014 - Updated DDR3 CKE requirement

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34556 MIG Virtex-6 DDR2/DDR3 - Termination and I/O Standard Guidelines N/A N/A
AR# 36104
Date Created 11/29/2010
Last Updated 06/06/2014
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG