AR# 36883


MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center - Design Assistant - Can multiple banks be open at the same time? If so, how many?


The 7 Series and Virtex-6 FPGA MIG DDR2/DDR3 design assigns user interface requests to bank machines. 

A bank machine is not assigned to a physical DRAM bank, rather a specific read/write request from the user/native interface. 

The number of bank machines in a design is four by default, but can be configured as two through to eight.

The number of bank machines, the traffic sent from the user interface, and specific JEDEC timing parameters affect the number of banks that can be open at a given time.

For further information on bank machines, see (Xilinx Answer 36505).


Note: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243)

The Xilinx MIG Solution Center is available to address all questions related to MIG. 

Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Generally, the design can keep one less bank open than the number of bank machines.

For example, if the design has five bank machines, four DRAM banks can be open at the same time. 

However, this is dependent on additional factors.


One factor is the traffic pattern coming from the user interface.

If the traffic targets the same row within the banks relatively continuously, the banks stay open. 

A bank only stays open if there is an accepted, but pending user request that targets the same bank and row and tRAS has not expired. 

When tRAS expires, the bank must be closed.


Additionally, the number of banks that can be opened consecutively is limited by the JEDEC requirement that "No more than four banks can be activated in a rolling tFAW window." 

If more than four banks are accessed within the tFAW window, a precharge to the last accessed bank must be issued to avoid a tFAW violation. 

It is possible to open more than four banks and avoid a tFAW violation if enough commands are requested to a bank consecutively.

For example, requesting one BL8 read to B0R0 (Bank 0 Row 0), B1R0, B2R0, B3R0, B4R0, B5R0, B6R0, B7R0 would cause a violation.  

However, requesting two consecutive BL8 reads to each of the eight banks would not cause a tFAW violation because the open bank requests are further spaced and span two rolling tFAW windows.

In this case, all eight banks can be opened if there are sufficient bank machines.

Note: It is possible to set up sequences such as two consecutive burst-8 reads to each bank and row that rotates through a number of banks where the pre-charge and activate times are hidden and there are no penalties for closing the banks. 

The sequences that allow this depend on the frequency of operation and the timing of the device. 

For example, at higher frequencies it might be possible to rotate through four banks with a burst-8 read, but this is not possible with a burst-8 write due to the DRAM timings at 1066 Mb/s. 

However, two burst-8 writes at each row/bank allows similar operation to the read case.

The best way to determine how many banks can remain open is to simulate the generated MIG design using your target access pattern. 

Depending on your access pattern, increasing the number of bank machines might allow more banks to remain open. 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34243 Xilinx Memory Interface Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36505 MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center Design Assistant - Bank Machines N/A N/A
AR# 36883
Date 08/19/2014
Status Active
Type Solution Center
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