AR# 37171

7 Series, Virtex-6/-5/-4, Spartan-6 - How do you enable internal Differential Termination?


How do you enable Differential Termination for true differential input IOSTANDARDs?


You can enable internal DIFF_TERM in the following ways:

Enable DIFF_TERM in HDL Code. 

The Language Templates and device Libraries Guide contain the instantiation template for the IBUFDS/IBUFGDS which contains an attribute DIFF_TERM that is set to TRUE to enable the DIFF_TERM.

Example VERILOG Instance:

.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
) IBUFDS_inst (
.O(O), // Buffer output
.I(I), // Diff_p buffer input (connect directly to top-level port)
.IB(IB) // Diff_n buffer input (connect directly to top-level port)

Example VHDL:

generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
port map (
O => O, -- Buffer output
I => I, -- Diff_p buffer input (connect directly to top-level port)
IB => IB -- Diff_n buffer input (connect directly to top-level port)

Enable DIFF_TERM in UCF. 

The DIFF_TERM constraint syntax is documented in the Constraints Guide.

For example:

INST "IO block name" DIFF_TERM = "{TRUE|FALSE}" ;

Enable DIFF_TERM in XDC.

You can see the syntax for this constraint in the Vivado Constraints Guide. 

For example:

set_property DIFF_TERM TRUE  [get_ports SYS_CLK_P]

The property can be set in the Vivado or PlanAhead GUI. You should select the input pair from the port list. There is a checkbox under properties that allows this to be set. 


Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
47499 SelectIO Design Assistance - Setting up on-chip termination in software N/A N/A
AR# 37171
Date 04/05/2017
Status Active
Type General Article
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