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AR# 37522

11.5 XST: FIFO36 usage is not reported in the BRAM section of the XST report

Description

When I use FIFO36, XST synthesis report does not report this block as using BRAM. Why?

Solution

This is a reporting error in XST for Virtex-5 and older devices.

WHAT NEXT:

1) The correct resource usage can been seen in the MAP report.

2) This issue is fixed in new XST parser for Virtex-6 and newer devices. If you want to turn on this parser for older devices, startingin ISE 12.2 software you canset the following switch in the .xst file or in other command line optionsfor synthesis properties in ISE GUI"-use_new_parser yes"

Option 2 : Is not recommended to use new parser for older devices unless advised by Xilinx Technical support. Since Xilinx has limited testing for older devices on the new parser.

EXAMPLE:

Old Parser:

Design Statistics
# IOs : 117

Cell Usage :
# BELS : 6
# GND : 2
# LUT2 : 1
# LUT3 : 1
# VCC : 2
# FlipFlops/Latches : 1
# FDC : 1
# RAMS : 1
# RAMB36_EXP : 1
# Clock Buffers : 4
# BUFGP : 4
# IO Buffers : 113
# IBUF : 59
# OBUF : 54
# Others : 1
# FIFO36_EXP : 1



NewParser:



Primitive and Black Box Usage:
------------------------------
# BELS : 6
# GND : 2
# LUT2 : 1
# LUT3 : 1
# VCC : 2
# FlipFlops/Latches : 1
# FDC : 1
# RAMS : 2
# FIFO36_EXP : 1
# RAMB36_EXP : 1
# Clock Buffers : 4
# BUFGP : 4
# IO Buffers : 113
# IBUF : 59
# OBUF : 54


AR# 37522
Date Created 10/08/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
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Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
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